1. Field of the Invention
This invention relates to electronic memory circuits, and more particularly, to a non-volatile memory circuit capable both of volatile dynamic RAM storage and non-volatile static ROM storage.
2. Description of the Prior Art
One of the disadvantages of semiconductor RAMs (random access memories) is their volatile nature. These memory devices retain their information only as long as power is supplied to them. However, as soon as power is lost, the stored information is also lost.
Different types of ROMs (read only memories) are used for information which is required to be stored in a non-volatile memory. Recently EPROMs (erasable programmable read only memories) and EEPROMs (electrically erasable programmable read only memories) have become widely available. In an EPROM the user may program the device electrically and erase the entire device by exposing it to ultraviolet light. In an EEPROM the device is programmable and erasable electrically.
While these devices have the desired features of non-volatility, they are somewhat more inconvenient to use than a RAM. The EPROM and EEPROM require higher voltages to program (or WRITE) the device than the operating semiconductor RAMs. Furthermore, high voltages are required to erase information from the EEPROM. The EPROM requires removal of the device from the system for exposure to ultraviolet light. Thus these non-volatile devices do not have the ease by which a RAM can store and change the stored information.
This inconvenience was circumvented by designing a memory cell including a shadow static non-volatile memory portion connected in parallel with a volatile memory portion. A fast WRITE is accomplished by a WRITE into the volatile (dynamic) RAM portion of the memory cell while the non-volatile portion is used for more permanent storage.
A typical shadow static memory cell includes nine transistors and seven access lines, of which six transistors are the standard static memory cell and the additional three transistors and one capacitor are used in the non-volatile portion of the cell. A detailed description of such a memory cell is presented in an article by R. Klein et al. entitled "Five Volt Only, Non-Volatile RAM Owes It All To Polysilicon," Electronics, Oct. 11, 1979, pp. 111-116. The large number of circuit elements required to implement a typical shadow static memory cell results in a low density memory circuit.
One way to improve the density of the memory circuit is to replace the static portion of the memory cell by a dynamic memory circuit. In U.S. patent application Ser. No. 558,647 by Rinerson et al. there is disclosed such a cell. This cell includes only two transistors, three capacitors, and three lines. This cell uses a floating gate structure to vary the capacitance of the cell depending on whether the floating gate is charged or discharged. A memory circuit incorporating this cell requires a dummy cell having two capacitors for utilization in sensing either the volatile or the non-volatile data stored in the memory cell.
The presence of the dummy capacitors in that system results in a memory cell having a large area and limits the use of the cell in systems requiring very densely packed small scale memories.
Additionally, existing systems lack the capability of simultaneously transferring information from the non-volatile to the volatile portion of each cell of the memory circuit in a bulk mode RECALL operation. This capability is important, for example, if an unexpected powerdown erases the DRAM and it is desired to transfer a complete start up program from the non-volatile memory.
Accordingly, a great need exists for non-volatile dynamic RAM (NVDRAM) memory circuit that may be scaled for future products and is capable of performing a bulk mode RECALL operation.